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U.S., ARMENIAN INVENTORS DEVELOP STAND-ALONE MEMORY DEVICE
US Fed News
December 15, 2006 Friday 1:34 AM EST
ALEXANDRIA, Va., Dec. 15 -- Gevorg Torjyan, Albert Harutyunyan and
Valery Vardanian, all from Yerevan, Armenia, and Yervant Zorian
of Santa Clara, Calif., have developed an apparatus, a method,
and a system to allocate redundant components with subsets of the
redundant components.
According to the U.S. Patent & Trademark Office: "In general,
various methods, apparatuses, and systems are described in which
logic executes, in series, a plurality of repair algorithms to
generate a repair signature for a memory. The memory has a full set
of redundant components associated with the memory. At least one or
more of the repair algorithms employ a subset of redundant components
that contains less than all of the redundant components in the full
set when attempting to generate the repair signature."
The inventors were issued U.S. Patent No. 7,149,921 on Dec. 12.
The patent has been assigned to Virage Logic Corp., Fremont, Calif.
The original application was filed on
Sept. 6, 2002, and is available at:
http://patft.uspto.gov/netacgi/nph-Parser?Sect 1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=% 2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G& ;l=50&s1=7,149,921.PN.&OS=PN/7,149,921& ;RS=PN/7,149,921.
For more information about US Fed News federal patent awards please
contact: Myron Struck, Managing Editor/US Bureau, US Fed News, Direct:
703/866-4708, Cell: 703/304-1897, [email protected].
US Fed News
December 15, 2006 Friday 1:34 AM EST
ALEXANDRIA, Va., Dec. 15 -- Gevorg Torjyan, Albert Harutyunyan and
Valery Vardanian, all from Yerevan, Armenia, and Yervant Zorian
of Santa Clara, Calif., have developed an apparatus, a method,
and a system to allocate redundant components with subsets of the
redundant components.
According to the U.S. Patent & Trademark Office: "In general,
various methods, apparatuses, and systems are described in which
logic executes, in series, a plurality of repair algorithms to
generate a repair signature for a memory. The memory has a full set
of redundant components associated with the memory. At least one or
more of the repair algorithms employ a subset of redundant components
that contains less than all of the redundant components in the full
set when attempting to generate the repair signature."
The inventors were issued U.S. Patent No. 7,149,921 on Dec. 12.
The patent has been assigned to Virage Logic Corp., Fremont, Calif.
The original application was filed on
Sept. 6, 2002, and is available at:
http://patft.uspto.gov/netacgi/nph-Parser?Sect 1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=% 2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G& ;l=50&s1=7,149,921.PN.&OS=PN/7,149,921& ;RS=PN/7,149,921.
For more information about US Fed News federal patent awards please
contact: Myron Struck, Managing Editor/US Bureau, US Fed News, Direct:
703/866-4708, Cell: 703/304-1897, [email protected].