U.S., ARMENIAN INVENTORS DEVELOP MEMORY REPAIR DATA SIZE REDUCTION METHOD
US Fed News
August 21, 2008 Thursday 4:07 AM EST
ALEXANDRIA, Va., Aug. 21 -- Yervant Zorian of Santa Clara, Calif.,
Karen Darbinyan of Fremont, Calif., and Gevorg Torjyan of Yerevan,
Armenia, have developed a self-repairable memory.
An abstract of the invention, released by the U.S. Patent & Trademark
Office, said: "Various methods and apparatuses are described in which
a repair data container may store a concatenated repair signature for
multiple memories having one or more redundant components associated
with each memory. A processor contains redundancy allocation logic to
execute one or more repair algorithms to generate a repair signature
for each memory. The repair data container may store actual repair
signatures for each memory having one or more defective memory cells
detected during fault testing and dummy repair signatures for each
memory with no defective memory cells. The processor may contain logic
configured to compress an amount of bits making up the concatenated
repair signature, to decompress the amount of bits making up the
concatenated repair signature, and to compose the concatenated
repair signature for all of the memories sharing the repair data
container. The repair data container may have an amount of fuses to
store the actual repair signatures for an adjustable subset of the
multiple memories."
The inventors were issued U.S. Patent No. 7,415,640 on Aug. 19.
The patent has been assigned to Virage Logic Corp., Fremont.
US Fed News
August 21, 2008 Thursday 4:07 AM EST
ALEXANDRIA, Va., Aug. 21 -- Yervant Zorian of Santa Clara, Calif.,
Karen Darbinyan of Fremont, Calif., and Gevorg Torjyan of Yerevan,
Armenia, have developed a self-repairable memory.
An abstract of the invention, released by the U.S. Patent & Trademark
Office, said: "Various methods and apparatuses are described in which
a repair data container may store a concatenated repair signature for
multiple memories having one or more redundant components associated
with each memory. A processor contains redundancy allocation logic to
execute one or more repair algorithms to generate a repair signature
for each memory. The repair data container may store actual repair
signatures for each memory having one or more defective memory cells
detected during fault testing and dummy repair signatures for each
memory with no defective memory cells. The processor may contain logic
configured to compress an amount of bits making up the concatenated
repair signature, to decompress the amount of bits making up the
concatenated repair signature, and to compose the concatenated
repair signature for all of the memories sharing the repair data
container. The repair data container may have an amount of fuses to
store the actual repair signatures for an adjustable subset of the
multiple memories."
The inventors were issued U.S. Patent No. 7,415,640 on Aug. 19.
The patent has been assigned to Virage Logic Corp., Fremont.